The demand for faster, higher density, random access memory integrated circuits is ever present. In the quest to meet this demand, numerous alternatives to the standard DRAM architecture have been proposed. Unfortunately, the higher density and higher speed requirements have largely proven to be mutually exclusive. Circuitry to accelerate data flow tends to add area to the memory device, which in turn adds cost. The higher cost of high speed devices has prevented their wide spread use, and therefore only limited quantities are manufactured. This limited manufacture further prevents the reduction in cost which typically can be accomplished through the manufacturing improvements and efficiencies associated with a high volume product. Ultra dense device architectures often require complex sequences of timing signals to access data in the array. These complex sequences add overhead to the access time creating a relatively slow device. The speed penalties associated with these architectures have likewise prevented their wide spread acceptance. A demand remains for a high speed, high density memory device that can compete with the standard DRAM in terms of the cost of manufacture and ease of use.